Conventional solid state random access memory devices are dominated by silicon dynamic random access memory (DRAM) devices which comprise a silicon substrate having a plurality of doped silicon layers into which are formed a plurality of memory elements, typically field effect transistors. Such memory devices are common in many applications for storage of volumes of data up to tens of megabytes, and have an advantage of relatively quick access times.
For storage of larger volumes of data, of the order of Gbytes upwards, rotating disc drives are common, but have reduced access times compared to silicon dynamic random access memory chips.
As well as the above prior art types of memory storage device, there is being developed by the assignees a class of solid magnetic random access memory (MRAM) storage components comprising a two-dimensional array of magnetic memory elements fabricated on top of a silicon substrate. Typically, each individual MRAM component may store between 32 megabytes, and 256 megabytes of data. Data is stored by first presenting the component with a segment address to identify where within the component the data is to be stored. Each MRAM component comprises a plurality of MRAM elements, which are cells within the component capable of storing a single bit of information. A plurality of MRAM components can be assembled into a MRAM device. Within a MRAM component, a plurality of MRAM elements are arranged into an MRAM segment sharing a common address. A segment is the minimum quantity of data which can be stored to or retrieved from an MRAM component Due to the cost of MRAM components, they may be used in applications where a conventional silicon dynamic random access memory (DRAM) is too small, but a conventional hard disk solution is too slow.
Problems found in MRAM components include:                MRAM components yield a physical address range which is not a power of two. An MRAM device comprising an array of MRAM components will therefore yield a non-contiguous physical address range.        A number of segments within each storage component of a MRAM device is not a power of two, which means a block address cannot be directly presented onto a binary signal row/segment address bus.        Each MRAM component may have numerous manufacturing defects which render many of its segments unusable.        MRAM component may degrade during their life so that further segments become unusable.        
It could be arranged that the physical addresses of the MRAM components are overlapped, such that a contiguous physical address range is provided, however this has a disadvantage of trading off other performance aspects of an MRAM device.
In the field of silicon random access memories, the problem of individual defective memory storage elements in a two dimensional array of memory storage elements is known. In U.S. Pat. No. 5,862,314 there is disclosed a computer system having a memory requester component which interfaces with a memory module. An error map which identifies a defective memory portion of the memory module is created and is stored in the computer system. Using this error map, a re-mapping table is provided which maps each of a plurality of defective memory portions to a non-defective memory portion in the memory module. When access to a requested portion of the memory module is made, the nor map is used to determine whether the requested memory portion in the memory module is on of a plurality of defective memory portions. If the error map indicates that the requested memory portion is one of the defective memory portions, then a determination is made from the re-mapping table, of a non-defective memory portion to which the requested memory portion is mapped.
In that scheme, each requested memory address contained in the request made by a computer is mapped to the corresponding respective physical memory address of the memory module, where that physical address contains non-damaged memory elements. However, where damaged memory elements are provided, the data destined for the physical addresses of those defective memory elements is re-directed to a redundant array of memory elements provided specifically for the purpose. In that known scheme, correctly operating memory elements do not have their physical addresses re-mapped. Defective memory elements retain their physical address, but the request for that physical address is re-mapped onto a new correctly operating memory element provided in a redundant array of memory elements. In the case of U.S. Pat. No. 5,168,324, an error map is used which effectively stores addresses of bad locations in the memory array and offers a substitute address. Methods such as disclosed in U.S. Pat. No. 5,168,324 have been known in hard disk drive technology for many years.
In U.S. Pat. No. 5,359,570, them is disclosed a solid state data storage device which receives a logical address from a computer system and provides a mapping to a physical address on a data storage device. Through use of a mapping between logical and physical addresses, defective sectors in a memory unit can be mapped out and fresh unused defect free sectors replace the defective sectors, automatically and without user intervention. In an address map between physical and logical addresses, each logical sector in it contains a physical address. There is created a defect map, which maps addresses of individual defective data storage elements in the memory array. A logical to physical address map provides a unique one to one mapping between logical and physical addresses, with any defects in the physical memory array being taken care of by a physical defect map which re-maps logical addresses to new physical addresses in a redundant army of memory elements to replace the defective memory elements in a main array.
Each of the above two disclosures address a similar problem in using a prior art solid data storage device, effectively as a substitute for a hard disc drive device. In each of the above disclosures, the mapping of logical to physical addresses is provided on a per chip basis. In each of the above two disclosures it is required that a separate redundant army of memory elements is provided in addition to a main array of memory elements.
Each of the above two devices address only the problem of defect avoidance. Neither of the above two disclosures address the problem encountered when discontinuities appear in ranges of physical addresses.
In the case of U.S. Pat. No. 5,359,570, instead of using an error map, an address translator device is used where a logical address is fed into one side, and a physical address is addressed at another side. The defect map data is stored in the actual memory device itself, using up part of the memory. In theory, such a system could be used to avoid address discontinuities, however a disadvantage of this scheme is that it involves a one for one mapping between individual logical addresses and individual physical addresses, which is very memory intensive. Using the method disclosed in U.S. Pat. No. 5,359,570, an address translation data storage table can become impractical and non-scaleable and is therefore suitable only for small numbers of physical memory addresses. The amount of memory capacity required to store the address mapping data table in the address translator is approximately 0.5% of the size of the memory which the address table is used with. This scheme is unsuitable for application for large memory capacities as are found in MRAM devices.